(1) Field of the Invention
The present invention relates to an emitter coupled logic (ECL) circuit which, more particularly to an ECL circuit receives two complementary input logic signals and is controlled by a set input signal.
(2) Description of the Prior Art
An ECL circuit is comprised of a differential amplifier. Therefore, it is possible to achieve very high speed operation. A recent trend has been for the application of an ECL circuit to a logic gate. In one proposal for such an application, the ECL circuit is provided with a set circuit. If the ECL circuit operates as a gate for passing of a certain logic input signal therethrough, the set circuit functions to selectively control the passing therethrough of the logic input signal. For example, if the set input signal (C) has logic "L" (low), the set circuit will allow the logic input signal (A) to pass through the ECL circuit, while if the set input signal (C) has logic "H" (high), the set circuit will not allow the logic input signal (A) to pass through the ECL circuit.
In usual ECL circuits, one side of the differential amplifier comprising the ECL circuit receives the logic input signal, while the other side receives a reference voltage signal (V.sub.ref). In recent years, however, it has been proposed to apply to the other side, instead of the reference voltage signal (V.sub.ref), a complementary input signal A with respect to the logic input signal A. Use of the complementary logic input signals (A, A) enlarges the difference between the two control input signals to (A-A) and, accordingly, offers the advantages of increased noise margin and further high speed operation. When the signals A and A are used as the control input signals for the differential amplifier, the amplifier can be driven by a control input signal having a magnitude of, for example, 400 mV.
There are problems, however, with the prior art ECL circuit during the set operation. Specifically, the ECL circuit often fails to be set when it is supposed to be set or is unintentionally set when it is supposed to be set. The reason for this will be explained hereinafter. In any case, this results in reduced reliability of operation of the ECL circuit and necessitates externally and forcibly fixing the set input signal to a suitable level.